A prior art digital Delta-Sigma converter is disclosed in the article entitled "A 3-.mu. CMOS Digital Codec with programable Echo Cancellation and Gain Setting" by P. Defraeye et al, published in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. SC-20, No. 3, June 1985, pp. 679 to 687.
In this known converter both the first and second integrator circuits operate at a frequency which is a multiple of the frequency of the input signal. Furthermore, each of the integrator circuits includes an internal feedback circuit coupled to a digital subtracting circuit so as to retain the information contained therein. When this known converter circuit is in its idle start condition and an input signal equal to zero is applied to it, the output signal of the circuit assumes an idle condition too, however, when the input signal becomes equal to zero after having been non-zero for some time the output signal will not exactly follow the input signal due to the presence in the circuit of previous information.